There are two toplevel schematics here:

uselib.sch: This schematic tests out all my hierarchical schematics
(buffer_1.sch, buffer_fix_power_1.sch, or8_1.sch, porttest-1.sch)

multipage_1.sch, multipage_2.sch: I had to try out a multipage schematic
to see if it worked


Problems that I've encountered:

If a library component is broken and you want to make your own version, you
can copy it into your directory and you MUST rename it.  Then you can 
edit the component, save it, and instantiate your own version.  If you
don't rename it, when you save and restore the parent schematic, it will
revert back to the broken library component.

Gnetlist cannot handle subschematics which connect two ports internally.
If port A is connected to port B in a subschematic, the nodes connected
to those ports should be merged in the parent module.  Or at minimum
it should warn you that this technique is not supported.

The recommended way to connect components to power and ground in the netlist
is to use net attributes such as net=Vcc:14 and net=Gnd:7.  These work
well for modules which are instantiated in the top level schematic.  However,
if you draw a subschematic that contains a 7400 gate, for example, that
has net=Vcc:14, then you will get a LOCAL net called U1/Vcc or U1/Gnd.
I believe the net= nodes should be treated as GLOBAL node names, not
local node names.  If you want a local node name, you should draw an output
pin and connect a wire to it in the parent module.
